The traditional circuit bias and sizing method using square law, as described in textbooks, is cumbersome and not very accurate in today’s sub-micron technologies. Unfortunately, the prevalent textbooks being rather old, still teach the square law method.
A more modern method using “gm/Id” of the transistor has been known since 1996 (Silviera, et. al. 1996), but hasn’t made its way into many designers’ toolkits. Instead of trying to explain it here, I suggest reading Bernhard E Boser’s (2011) lecture notes.
If you’d like to try this yourself, I have created an example testbench for ngspice using 45nm predictive technology models from ASU and a python script to post-process it.
If you find an error, have an idea for improving it, or just want to discuss this generally, please leave a reply or contact me.